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style selection becomes important. The glass style and subsequent resin content will have different effects on the nominal thickness obtained. Conductor width (W) The finished width of the conductor can produce variance, which is likely to occur from lot to lot. Therefore, process control measures are necessary when producing controlled impedance circuits. The density of neighboring circuits will have an effect on the final etch. Often it is advantageous to modify the artwork line width at phototool generation for predicted variance. Dielectric constant (Dk) Choosing a laminate resin system with a consistent dielectric constant has an influence on characteristic impedance over higher frequencies. The influence of dielectric constant becomes most critical when the ML-PWB design is a high-layer-count design. The lower the Dk value of the resin system, the thinner the overall board can be. Typically, the manufacturer has little opportunity to affect the dielectric constant, because the material type is specified by the design. Here, it is important that the designer/manufacturer know the Dk value range of the laminate supplier s resin system. Caution: Do not use the Dk value of the neat resin, but that of the composite laminate, which will vary somewhat with glass style. This is sometimes referred to as effective Dk (Eff Dk). Conductor thickness (T) The conductor thickness or copper weight can also affect the final impedance value. Here, as with conductor width, manufacturing process variations can have an inverse effect on the precision of the impedance value. Some modern software simulation tools, such as those from Polar Instruments, Inc., allow values for conductor profile (area) to be included in the simulation. This is more significant when lines are of heavy copper. It is best to avoid routing of impedance lines on plated subcores due to the added variability.

The input capture register is a 16-bit read-only register. When the rising or falling edge (according to the input capture edge setting, ICES1) of the signal at the input capture pin, ICP, is detected, the current value of the Timer/Counter1 is transferred to the Input Capture Register, ICR1. At the same time, the input capture flag, ICF1, is set to 1. Since the Input Capture Register, ICR1, is a 16-bit register, a temporary register TEMP is used when ICR1 is read to ensure that both bytes are read simultaneously. When the CPU reads the low-byte ICR1L, the data is sent to the CPU and the data of the high-byte ICR1H is placed in the TEMP register. When the CPU reads the data in the high-byte ICR1H, the CPU receives the data in the TEMP register. Consequently, the low-byte ICR1L must be accessed first for a full 16-bit register read operation. The TEMP register is also used when accessing TCNT1 and OCR1A. If the main program and also interrupt routines perform access to registers using TEMP, interrupts must be disabled during access from the main program or interrupts if interrupts are re-enabled. (Figure 3.20.)

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For external impedance tracks and internal plated-up tracks such as on subcores, autothieving patterns will minimize large variations in plating height between tracks in dense areas and those in uncongested areas This will increase the fabricator s ability to produce impedance values consistently within a smaller range 2734 Sequential Laminations When a design includes buried and/or blind vias, it typically requires a set of sequential lamination and plating cycles These technologies are defined in the industry design standard IPC- 2221/2222 and are known as Type 4 ML-PWBs These build types, when employing industry standard feature sizes, are mature in the industry Complementing technologies, employing use of sequential processes for ML-PWB designs containing microvias less than 015 mm, are considered as build-up technologies The terminology of build-up technologies encompasses many design stack-up variations; they can take on many forms and employ a multitude of methods.

is reversed, the direction of movement will also be reversed This gives a linear movement to the carriage, which is attached to the screw These drives have a high load-carrying capacity even though the nut and screw transmission is compact The other advantages of this drive are simplicity, ease of manufacture and possibility of attaining a slow and uniform movement on the operative member

The build-up technologies defined in IPC-2315 and IPC-2221/2226 include categories named Type I, II, III, IV, V, and VI The advanced build-up technologies use the materials found in IPC-4104 These include materials for layer forming, dielectric insulation, and interconnectivity Included are photo-imageable and non-photo-imageable materials (liquid, paste, or dry-film nonreinforced dielectric); adhesive-coated dielectrics (reinforced and nonreinforced); and conductive foils and paste (coated and non-coated, photo-imageable) For a detailed discussion of these processes, see Chap 22 and 23 This discussion will limit itself to addressing processes for standard technology Type 4 and advanced technology build-up Types I, II, and III, which can be manufactured with conventional processes 27341 The Buried Via Stack-Up To avoid hopelessly complex routing, each signal net is generally routed using only one pair of layers with what is called Manhattan geometry.

This means that diagonal routing is avoided and all signal lines run in a horizontal or a vertical direction To avoid blockage and side-to-side cross-talk problems, horizontal lines are run on.

one layer and vertical lines on the other This means that, in addition to a via at each end of the net (I/O via), most nets need one or two additional vias (routing vias) to change direction from horizontal to vertical Figure 2714 shows an example of Manhattan geometry The net shown in Fig 2714 has two I/O vias and two routing vias The I/O vias connect the signal lines to the board surface, where the net connects to an input or output point of an active circuit The routing vias are used to change directions from horizontal to vertical With through-hole vias, the routing vias pass through all layers, consuming valuable routing space A high-layer-count board with many signal layer pairs can run out of via sites In this case, additional layers will not improve routing completion and the board is said to be via-starved.

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